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CS4340 24-Bit, 96 kHz Stereo D/A Converter for Audio
Features
! 101 ital-to-analog conversion, digital de-emphasis and switched capacitor analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter. The CS4340 accepts data at audio sample rates from 4 kHz to 100 kHz, consumes very little power, and operates over a wide power supply range. The features of the CS4340 are ideal for DVD players, CD players, set-top box and automotive systems. ORDERING INFORMATION CS4340-DSZ 16-pin SOIC, Lead Free, CS4340-KS 16-pin SOIC CS4340-KSZ 16-pin SOIC, Lead Free, CS4340-CZZ 16-pin TSSOP, Lead Free, CDB4340 Evaluation Board
dB Dynamic Range ! -91 dB THD+N ! +3.0 V or +5.0 V Power Supply ! Low Clock Jitter Sensitivity ! Filtered Line-level Outputs ! On-chip Digital De-emphasis for 32, 44.1 and 48 kHz ! 33 mW with 3V Supply ! Popguard(R) Technology for Control of Clicks and Pops ! Lead-free Packaging Available
Description
The CS4340 is a complete stereo digital-to-analog system including digital interpolation, fourth-order delta-sigma digI
-40 to 85 C -10 to 70 C -10 to 70 C -10 to 70 C
SCLK/DEM1 RST
DEM0
MUTEC External Mute Control DAC Analog Filter AOUTL
De-emphasis Interpolation Filter Interpolation Filter
LRCK SDATA
Serial Input Interface
DAC
Analog Filter
AOUTR
DIF0 DIF1
MCLK
www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved)
JULY '05 DS297F3 1
CS4340
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 4 SPECIFIED OPERATING CONDITIONS .............................................................................................. 4 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 4 ANALOG CHARACTERISTICS (CS4340-KS/KSZ/CZZ)....................................................................... 5 ANALOG CHARACTERISTICS (CS4340-DSZ) .................................................................................... 7 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE........................................ 8 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE........................................................ 11 SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK ..................................................... 12 DC ELECTRICAL CHARACTERISTICS.............................................................................................. 13 DIGITAL INPUT CHARACTERISTICS ................................................................................................ 13 DIGITAL INTERFACE SPECIFICATIONS........................................................................................... 13 2. PIN DESCRIPTION .............................................................................................................................. 14 3. TYPICAL CONNECTION DIAGRAM ................................................................................................. 15 4. APPLICATIONS ................................................................................................................................... 16 4.1 Sample Rate Range/Operational Mode ........................................................................................ 16 4.2 System Clocking ........................................................................................................................... 16 4.2.1 Internal Serial Clock Mode ............................................................................................... 16 4.2.2 External Serial Clock Mode .............................................................................................. 17 4.3 Digital Interface Format ................................................................................................................. 17 4.4 De-Emphasis ................................................................................................................................ 18 4.5 Power-up Sequence .................................................................................................................... 19 4.6 Popguard(R) Transient Control ........................................................................................................ 19 4.6.1 Power-up .......................................................................................................................... 19 4.6.2 Power-down ..................................................................................................................... 19 4.6.3 Discharge Time ................................................................................................................ 19 4.7 Mute Control ................................................................................................................................. 20 4.8 Grounding and Power Supply Arrangements ............................................................................... 20
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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5. PARAMETER DEFINITIONS ................................................................................................................21 6. REFERENCES ......................................................................................................................................22 7. PACKAGE DIMENSIONS ....................................................................................................................23 7.1 SOIC ..............................................................................................................................................23 7.2 TSSOP ..........................................................................................................................................24 8. PACKAGE THERMAL RESISTANCE .................................................................................................25
LIST OF FIGURES
Figure 1. Output Test Load ...........................................................................................................................6 Figure 2. Maximum Loading..........................................................................................................................6 Figure 3. Single-Speed Stopband Rejection .................................................................................................9 Figure 4. Single-Speed Transition Band .......................................................................................................9 Figure 5. Single-Speed Transition Band (Detail)...........................................................................................9 Figure 6. Single-Speed Passband Ripple .....................................................................................................9 Figure 7. Double-Speed Stopband Rejection................................................................................................9 Figure 8. Double-Speed Transition Band......................................................................................................9 Figure 9. Double-Speed Transition Band (Detail) .......................................................................................10 Figure 10. Double-Speed Passband Ripple................................................................................................10 Figure 11. Serial Input Timing (External SCLK) ..........................................................................................11 Figure 12. Internal Serial Mode Input Timing ..............................................................................................12 Figure 13. Internal Serial Clock Generation ................................................................................................12 Figure 14. Typical Connection Diagram......................................................................................................15 Figure 15. CS4340 Format 0 - I2S up to 24-Bit Data ..................................................................................17 Figure 16. CS4340 Format 1 - Left Justified up to 24-Bit Data ...................................................................17 Figure 17. CS4340 Format 2 - Right Justified, 24-Bit Data.........................................................................18 Figure 18. CS4340 Format 3 - Right Justified, 16-Bit Data.........................................................................18 Figure 19. De-Emphasis Curve...................................................................................................................18
LIST OF TABLES
Table 1.CS4340 Speed Modes ...................................................................................................................16 Table 2.Single-Speed Mode Standard Frequencies ...................................................................................16 Table 3.Double-Speed Mode Standard Frequencies..................................................................................16 Table 4.Internal SCLK/LRCK Ratio.............................................................................................................17 Table 5.Digital Interface Format - DIF1 and DIF0 .......................................................................................17 Table 6.De-Emphasis Control .....................................................................................................................18
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1. CHARACTERISTICS AND SPECIFICATIONS
(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics are derived from measurements taken at TA = 25C.)
SPECIFIED OPERATING CONDITIONS (All voltages with respect to AGND = 0 V.)
Parameters DC Power Supply Nominal 3.3V Nominal 5.0V Specified Operating Temperature (Power Applied) -KS/KSZ/CZZ -DSZ VA VA TA TA 2.7 4.75 -10 -40 3.3 5.0 3.6 5.5 +70 +85 V V C C Symbol Min Nom Max Units
ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to AGND. Operation
beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.) Parameters DC Power Supply Input Current Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature Notes: 1. Any pin except supplies.
(Note 1)
Symbol VA Iin VIND TA Tstg
Min -0.3 -0.3 -55 -65
Max 6.0 10 VA+0.4 125 150
Units V mA V C C
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ANALOG CHARACTERISTICS (CS4340-KS/KSZ/CZZ) (Test conditions (unless otherwise
specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load RL = 10 k, CL = 10 pF (see Figure 1).) VA = 5.0 V Parameter Single-Speed Mode Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit Fs = 48 kHz
(Note 2)
VA = 3.0 V Max Min Typ Max Unit
Min
Typ
unweighted A-Weighted unweighted A-Weighted
(Note 2)
93 96 -
98 101 92 95 -91 -78 -38 -90 -72 -32
-86 -
89 92 -
94 97 92 95 -94 -74 -34 -91 -72 -32
-89 -
dB dB dB dB dB dB dB dB dB dB
16-Bit
0 dB -20 dB -60 dB 0 dB -20 dB -60 dB Fs = 96 kHz
(Note 2)
Double-Speed Mode Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit
unweighted A-Weighted unweighted A-Weighted
(Note 2)
93 96 -
98 101 92 95 -91 -78 -38 -90 -72 -32
-86 -
89 92 -
94 97 92 95 -94 -74 -34 -91 -72 -32
-89 -
dB dB dB dB dB dB dB dB dB dB
16-Bit
0 dB -20 dB -60 dB 0 dB -20 dB -60 dB
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ANALOG CHARACTERISTICS (CS4340-KS/KSZ/CZZ)
Parameters Dynamic Performance for All Modes Interchannel Isolation (1 kHz) DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Output Characteristics and Specifications Full Scale Output Voltage Output Impedance Minimum AC-Load Resistance Maximum Load Capacitance
(Note 3) (Note 3)
(Continued) Typ 102 0.1 100 0.7*VA 100 3 100 Max 0.8*VA Units dB dB ppm/C Vpp k pF
Symbol
Min 0.6*VA -
RL CL
-
Notes: 2. One-half LSB of triangular PDF dither is added to data. 3. Refer to Figure 2. .
125 Capacitive Load -- C L (pF)
3.3 F AOUTx + V out R L C L
100 75 50 25 Safe Operating Region
AGND
2.5 3
5
10
15
20
Resistive Load -- RL (k )
Figure 1. Output Test Load
Figure 2. Maximum Loading
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ANALOG CHARACTERISTICS (CS4340-DSZ) (Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load RL = 10 k, CL = 10 pF (see Figure 1).)
VA = 5.0 V Parameter Single-Speed Mode Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit Fs = 48 kHz
(Note 2)
VA = 3.0 V Max Min Typ Max Unit
Min
Typ
unweighted A-Weighted unweighted A-Weighted
(Note 2)
93 96 -
98 101 92 95 -91 -78 -38 -90 -72 -32
-86 -
89 92 -
94 97 92 95 -94 -74 -34 -91 -72 -32
-87 -
dB dB dB dB dB dB dB dB dB dB
16-Bit
0 dB -20 dB -60 dB 0 dB -20 dB -60 dB Fs = 96 kHz
(Note 2)
Double-Speed Mode Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit
unweighted A-Weighted unweighted A-Weighted
(Note 2)
93 96 -
98 101 92 95 -91 -78 -38 -90 -72 -32
-86 -
89 92 -
94 97 92 95 -94 -74 -34 -91 -72 -32
-87 -
dB dB dB dB dB dB dB dB dB dB
16-Bit
0 dB -20 dB -60 dB 0 dB -20 dB -60 dB
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ANALOG CHARACTERISTICS (CS4340-DSZ) (Continued)
Parameters Dynamic Performance for All Modes Interchannel Isolation (1 kHz) DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Output Characteristics and Specifications Full Scale Output Voltage Output Impedance Minimum AC-Load Resistance Maximum Load Capacitance
(Note 3) (Note 3)
Symbol
Min 0.6*VA -
Typ 102 0.1 100 0.7*VA 100 3 100
Max 0.8*VA -
Units dB dB ppm/C Vpp k pF
RL CL
-
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.)
Parameter Single-Speed Mode - (4 kHz to 50 kHz sample rates) Passband to -0.05 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Passband Group Delay Deviation De-emphasis Error (Relative to 1 kHz)
(Note 5) (Note 4)
Min
Typ
Max
Unit
0 0 -0.02 0.5465 50 -
9/Fs 0.36/Fs -
0.4535 0.4998 +0.08 +0.05/-0.14
Fs Fs dB Fs dB s s dB
0 - 20 kHz Fs = 44.1 kHz
Double-Speed Mode - (50 kHz to 100 kHz sample rates) Passband to -0.1 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Passband Group Delay Deviation 0 - 40 kHz 0 - 20 kHz
(Note 4)
0 0 -0.06 0.577 55 -
4/Fs 1.39/Fs 0.23/Fs
0.4621 0.4982 +0.2 -
Fs Fs dB Fs dB s s s
Notes: 4. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs. 5. De-emphasis is only available in Single-Speed Mode.
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Figure 3. Single-Speed Stopband Rejection
Figure 4. Single-Speed Transition Band
Figure 5. Single-Speed Transition Band (Detail)
Figure 6. Single-Speed Passband Ripple
Figure 7. Double-Speed Stopband Rejection
Figure 8. Double-Speed Transition Band
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Figure 9. Double-Speed Transition Band (Detail)
Figure 10. Double-Speed Passband Ripple
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SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Parameters MCLK Frequency MCLK Duty Cycle Input Sample Rate LRCK Duty Cycle SCLK Pulse Width Low SCLK Pulse Width High SCLK Frequency SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time Single-Speed Mode Double-Speed Mode tslrd tslrs tsdlrs tsdh tsclkl tsclkh Single-Speed Mode Double-Speed Mode Fs Fs Symbol Min 1.024 45 4 50 40 20 20 20 20 20 20 Max 25.6 55 50 100 60 128xFs 64xFs Units MHz % kHz kHz % ns ns Hz Hz ns ns ns ns
LRCK t slrd t slrs t sclkl t sclkh
SCLK t sdlrs
SDATA
t sdh
Figure 11. Serial Input Timing (External SCLK)
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SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK
Parameters MCLK Frequency MCLK Duty Cycle Input Sample Rate LRCK Duty Cycle SCLK Period SCLK rising to LRCK edge tsclkr SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time MCLK / LRCK = 512, 256 or 128 SCLK rising to SDATA hold time MCLK / LRCK = 384 or 192 tsdlrs tsdh tsdh 1 --------------------- + 10 ( 512 )Fs 1 --------------------- + 15 ( 512 )Fs 1 --------------------- + 15 ( 384 )Fs t sclkw ------------2
(Note 7)
Symbol
Min 1.024 45
Typ (Note 6)
Max 25.6 55 50 100 -
Units MHz % kHz kHz % s
Single-Speed Mode Double-Speed Mode
Fs Fs tsclkw
4 50
1 --------------SCLK
-
-
s ns ns ns
-
Notes: 6. The Duty Cycle must be 50% +/- 1/2 MCLK Period. 7. See section 4.2.1 for derived internal frequencies.
LRCK t sclkr SDATA
t sclkw
t sdlrs *INTERNAL SCLK t sdh
Figure 12. Internal Serial Mode Input Timing *The SCLK pulses shown are internal to the CS4340.
LRCK
MCLK 1
*INTERNAL SCLK
N 2
N
SDATA
Figure 13. Internal Serial Clock Generation * The SCLK pulses shown are internal to the CS4340. N equals MCLK divided by SCLK 12 DS297F3
CS4340
DC ELECTRICAL CHARACTERISTICS
Parameters Normal Operation (Note 8) Power Supply Current Power Dissipation Power-down Mode (Note 9) Power Supply Current Power Dissipation All Modes of Operation Power Supply Rejection Ratio (Note 10) VQ Nominal Voltage Output Impedance Maximum allowable DC current source/sink Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink MUTEC Low-Level Output Voltage MUTEC High-Level Output Voltage Maximum MUTEC Drive Current 1 kHz 60 Hz PSRR 60 40 0.45*VA 250 0.01 VA 250 0.01 0 VA 3 dB dB V VA = 5.0 V VA = 3.0 V VA = 5.0 V VA = 3.0 V IA 60 30 0.3 0.09 A A mW mW VA = 5.0 V VA = 3.0 V VA = 5.0 V VA = 3.0 V IA IA 15 11 75 33 18 14 90 42 mA mA mW mW (AGND = 0 V; all voltages with respect to AGND.) Symbol Min Typ Max Units
k
mA V
k
mA V V mA
Notes: 8. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input sampled at the highest Fs for each speed mode, and open outputs, unless otherwise specified. 9. Power Down Mode is defined as RST = LO with all clocks and data lines held static. 10. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 14. Increasing the capacitance will also increase the PSRR.
DIGITAL INPUT CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.)
Parameters Input Leakage Current Input Capacitance Symbol Iin Min Typ 8 Max 10 Units A pF
DIGITAL INTERFACE SPECIFICATIONS
Parameters 3.3 V Logic (3.0 V to 3.6 V DC Supply) High-Level Input Voltage Low-Level Input Voltage 5.0 V Logic (4.75 V to 5.25 V DC Supply) High-Level Input Voltage Low-Level Input Voltage
(AGND = 0 V; all voltages with respect to AGND.) Symbol VIH VIL VIH VIL Min 2.0 2.0 Max 0.8 0.8 Units V V V V
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2. PIN DESCRIPTION
RST SDATA SCLK/DEM1 LRCK MCLK DIF1 DIF0 DEM0
1 2 3 4 5 6
7
16 15 14 13 12 11
10
MUTEC AOUTL VA AGND AOUTR REF_GND VQ FILT+
8
9
Pin Name
RST SDATA SCLK DEM1 DEM0 LRCK MCLK DIF1 DIF0 FILT+ VQ REF_GND AOUTR AOUTL AGND VA MUTEC
# 1 2 3 3 8 4 5 6 7 9 10 11 12 15 13 14 16
Pin Description
Reset (Input) - Powers down device. Serial Audio Data (Input) - Input for two's complement serial audio data. Serial Clock (Input) -Serial clock for the serial audio interface. De-emphasis Control (Input) - Selects the standard 15 s/50 s digital de-emphasis filter response for 44.1 kHz sample rate. Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial Clock and Serial Audio Data. Positive Voltage Reference (Output) - Positive voltage reference for the internal sampling circuits. Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. Reference Ground (Input) - Ground reference for the internal sampling circuits. Analog Outputs (Output) - The full scale analog output level is specified in the Analog Characteristics table. Analog Ground (Input) Power (Input) - Positive power for the analog, digital and serial audio interface sections. Mute Control (Output) - Control signal for an optional mute circuit.
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3. TYPICAL CONNECTION DIAGRAM
+ 14 VA 0.1 F 1 F
+3.0 V to +5.0 V
2 Serial Audio Data Processor 3 4
SDATA SCLK/DEM1 LRCK CS4340 M UTEC 16 AOUT L 15
3.3 F + 10 k
560
Left Audio O utput C RL
External Clock
5
M CLK FILT+ VQ
9 10 .1 F + 1 F 11 0.1 F + 1 F
OPTIONAL MUTE CIRCUIT
6 7 Mode Configuration 8
DIF1 DIF0
REF_GND 3.3 F 12 AOUTR + 10 k AGND 13 C= C 560
DEM0 1 RST
Right Audio O utput RL R L + 560 4 F S R L 560
Figure 14. Typical Connection Diagram
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4. APPLICATIONS 4.1 Sample Rate Range/Operational Mode
The device operates in one of two operational modes determined by the Master Clock to Left/Right Clock ratio (see section 4.2). Sample rates outside the specified range for each mode are not supported.
Input Sample Rate (Fs) 4 kHz - 50 kHz 50 kHz - 100 kHz
MODE Single-Speed Mode Double-Speed Mode
Table 1. CS4340 Speed Modes
4.2
System Clocking
The device requires external generation of the master (MCLK) and left/right (LRCK) clocks. The device also requires external generation of the serial clock (SCLK) if the internal serial clock is not used. The LRCK, defined also as the input sample rate Fs, must be synchronously derived from MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio sample rates and the required MCLK frequency, are illustrated in Tables 2 and 3.
Sample Rate (kHz) 32 44.1 48
256x 8.1920 11.2896 12.2880
MCLK (MHz) 384x 12.2880 16.9344 18.4320
512x 16.3840 22.5792 24.5760
Table 2. Single-Speed Mode Standard Frequencies
Sample Rate (kHz) 64 88.2 96 MCLK (MHz) 128x 8.1920 11.2896 12.2880 192x 12.2880 16.9344 18.4320
Table 3. Double-Speed Mode Standard Frequencies
4.2.1 Internal Serial Clock Mode
The device will enter the Internal Serial Clock Mode if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK. In this mode, the SCLK is internally derived and synchronous with MCLK and LRCK. The SCLK/LRCK ratio is either 32, 48, or 64 depending upon the MCLK/LRCK ratio and the Digital Interface Format selection (see Table 4).
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The internal serial clock is utilized when additional de-emphasis control is required. Operation in the Internal Serial Clock mode is identical to operation with an external SCLK synchronized with LRCK; however, External SCLK mode is recommended for system clocking applications. Input MCLK/LRCK Ratio 512, 256, 128 384, 192 512, 256, 128
Digital Interface Format Selection Left Justified 24 Right Justified Right Justified Bits 24 Bits 16 Bits X X X X X X Internal SCLK/LRCK Ratio 32 48 64
I S up to 24 Bits X X -
2
Table 4. Internal SCLK/LRCK Ratio
4.2.2 External Serial Clock Mode
The device will enter the External Serial Clock Mode whenever 16 low to high transitions are detected on the SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial Clock Mode if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK.
4.3
Digital Interface Format
The device will accept audio samples in several digital interface formats as illustrated in Table 5. The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship between LRCK, SCLK and SDIN, see Figures 15 through 18.
DIF1 0 0 1 1 DIF0 0 1 0 1 DESCRIPTION
I2S, up to 24-bit data Left Justified, up to 24-bit data Right Justified, 24-bit Data Right Justified, 16-bit Data
FORMAT 0 1 2 3
FIGURE 15 16 17 18
Table 5. Digital Interface Format - DIF1 and DIF0
LR C K
Left C ha nnel
R ig ht C ha nnel
SCLK
SDIN
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 15. CS4340 Format 0 - I2S up to 24-Bit Data
LR C K Left C ha nnel R ig ht C ha nnel
SCLK
SDIN
MSB -1
-2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB -1
-2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 16. CS4340 Format 1 - Left Justified up to 24-Bit Data
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LRCK
Left Channel
R ight Cha nnel
SCLK
SDIN
0
23 22 21 20 19 18
7
6
5
4
3
2
1
0
23 22 21 20 19 18
7
6
5
4
3
2
1
0
32 clo cks
Figure 17. CS4340 Format 2 - Right Justified, 24-Bit Data
LRCK
Left Channel
R ight Cha nnel
SCLK
SDIN
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Figure 18. CS4340 Format 3 - Right Justified, 16-Bit Data 32 clo cks
4.4
De-Emphasis
The device includes on-chip digital de-emphasis. Figure 19 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Pin 8 is available for de-emphasis control and selects the 44.1 kHz de-emphasis filter. If the Internal Serial Clock is used, pin 3 is also available for additional de-emphasis control and, in combination with pin 8, selects either the 32, 44.1, or 48 kHz de-emphasis filter. Please see Table 6 for the desired de-emphasis control.
Gain dB T1=50 s 0dB
Internal SCLK
DEM1 0 0 1 1 DEM0 Description 0 Disabled 1 44.1 kHz 0 48 kHz 1 32 kHz
External SCLK DEM0 Description
0 1
Disabled 44.1 kHz
T2 = 15 s
-10dB
Table 6. De-Emphasis Control
F1 3.183 kHz F2 Frequency 10.61 kHz
Figure 19. De-Emphasis Curve
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4.5 Power-up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supply and configuration pins are stable, and the clocks are locked to the appropriate frequencies discussed in section 4.2. It is also recommended that reset be enabled if the analog supply drops below the minimum specified operating voltage to prevent power glitch related issues.
4.6
Popguard(R) Transient Control
The CS4340 uses Popguard(R) technology to minimize the effects of output transients during power-up and powerdown. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated inside the DAC when RST is enabled/disabled and requires no other external control, aside from choosing the appropriate DCblocking capacitors.
4.6.1 Power-up
When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing the power-up transient.
4.6.2 Power-down
To prevent transients at power-down, the device must first enter its power-down state by enabling RST. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR. In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on.
4.6.3 Discharge Time
To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking capacitors have fully discharged before turning on the power or exiting the power-down state. If not, a transient will occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the powerdown state is related to the value of the DC-blocking capacitance. For example, with a 3.3 F capacitor, the minimum power-down time will be approximately 0.4 seconds.
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4.7 Mute Control
The Mute Control pin goes high during power-up initialization, reset, or if the MCLK to LRCK ratio is incorrect. The pin will also go high following the reception of 8192 consecutive audio samples of static 0 or -1 on both the left and right channels. A single sample of non-zero data on either channel will cause the Mute Control pin to go low. This pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single-ended single supply system. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. See the CDB4340 data sheet for a suggested mute circuit.
4.8
Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4340 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 14 shows the recommended power arrangements, with VA connected to a clean supply. If the ground planes are split between digital ground and analog ground, REF_GND & AGND should be connected to the analog ground plane. Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and REF_GND (as well as VQ and REF_GND), and should also be located on the same layer as the DAC. The CDB4340 evaluation board demonstrates the optimum layout and power supply arrangements.
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5. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N) A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C.
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6. REFERENCES
1) CDB4340 Evaluation Board Datasheet
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7. PACKAGE DIMENSIONS 7.1 SOIC
16L SOIC (150 MIL BODY) PACKAGE DRAWING
E
H
1 b c
D SEATING PLANE e A1
A L
DIM A A1 b C D E e H L
MIN 0.053 0.004 0.013 0.0075 0.386 0.150 0.040 0.228 0.016 0
INCHES NOM 0.064 0.006 0.016 0.008 0.390 0.154 0.050 0.236 0.025 4
MAX 0.069 0.010 0.020 0.010 0.394 0.157 0.060 0.244 0.050 8 JEDEC #: MS-012
MIN 1.35 0.10 0.33 0.19 9.80 3.80 1.02 5.80 0.40 0
MILLIMETERS NOM 1.63 0.15 0.41 0.20 9.91 3.90 1.27 6.0 0.64 4
MAX 1.75 0.25 0.51 0.25 10.00 4.00 1.52 6.20 1.27 8
Controling Dimension is Millimeters
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CS4340
7.2 TSSOP
16L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11 A2 A1
L
E
A
e b
2
END VIEW
SIDE VIEW
123
SEATING PLANE
TOP VIEW
DIM A A1 A2 b D E E1 e L
MIN -0.002 0.03346 0.00748 0.193 0.248 0.169 -0.020 0
INCHES NOM -0.004 0.0354 0.0096 0.1969 0.2519 0.1732 0.026 BSC 0.024 4
MAX 0.043 0.006 0.037 0.012 0.201 0.256 0.177 -0.028 8
MIN -0.05 0.85 0.19 4.90 6.30 4.30 -0.50 0
MILLIMETERS NOM --0.90 0.245 5.00 6.40 4.40 0.065 BSC 0.60 4
NOTE MAX 1.10 0.15 0.95 0.30 5.10 6.50 4.50 -0.70 8
2,3 1 1
JEDEC #: MO-153 Controlling Dimension is Millimeters Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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8. PACKAGE THERMAL RESISTANCE
Package SOIC TSSOP
(for multi-layer boards) (for multi-layer boards)
Symbol JA JA
Min -
Typ 74 89
Max -
Units C/Watt C/Watt
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